Attainment of low interfacial trap density in Ge(100) and Ge(110) gate stacks via low-temperature grown epi-Si and direct high-κ deposition
Hsien-Wen Wan1*, Yi-Ting Cheng1, Chao-Kai Cheng1, Yu-Jie Hong1, Tien-Yu Chu1, Chien-Ting Wu2, Jueinai Kwo3, Minghwei Hong1
1Graduate Institute of Applied Physics and Department of Physics, National Taiwan University, Taipei, Taiwan
2Taiwan Semiconductor Research Institute, Hsinchu, Taiwan
3Department of Physics, National Tsing Hua University, Hsinchu, Taiwan
* Presenter:Hsien-Wen Wan,
The complementary metal-oxide-semiconductor (CMOS) technology in 3D-configured fin and gate-all-around (GAA) nano-sheets structures have used (100) and (110) orientations as the top/bottom surface and the sidewalls. This has made the two surfaces equally important for the MOS device performances. To incorporate Ge as the channel layer in replacing Si for its intrinsically high carrier mobility, attainment of low interfacial trap densities (Dit’s) in the high-κ/Ge(100) and high-κ/Ge(110) interfaces is vital to move the Fermi level efficiently across the Ge bandgap. In recent years, Si-cap proved to be the most practical method in passivating Ge with an acceptable Dit and small charge trapping. However, a high-pressure (20 atm) hydrogen annealing was necessary to lower the Dit from 1012 eV-1cm-2 to the range of 1011 eV-1cm-2 or lower.

To investigate the compatibility of the low-temperature grown epi-Si on Ge with the Fin- and GAA- field-effect-transistors (FETs) applications, we have directly deposited high-k on the low-temperature epi-Si on Ge(100) and Ge(110). The extracted Dit is in the range of 2-3 x 1011 eV-1cm-2 for the epi-Si/Ge(100) gate stacks, comparable to those attained in the state-of-the-art Ge(100) gate stacks. Moreover, we have achieved extremely low Dit values ~6 x 1010 eV-1cm-2 of epi-Si/Ge(110) gate stacks, the lowest ever reported in the Ge (110) gate stacks. The lower Dit achieved in (110) orientation than that in the (100) orientation (~2-3 x 1011 eV-1cm-2) might be attributed to less Ge segregation during the growth of epi-Si on Ge(110). For the low-temperature grown epi-Si/Ge gate stacks, conventional post metallization forming gas annealing (FGA), namely no need to employ the annealing under 20 atm hydrogen, has reduced the effective oxide trap density (ΔNeff) of one order of magnitude. We have achieved values lower than the one required of sufficient reliability (targeted ΔNeff ~3x1010 cm-2) at equivalent oxide fields (Eox) of ~10 MV/cm (i.e., larger than at operating condition). The C-V hysteresis measurements on the MOSCAPs with a stress at accumulation to access the equivalent oxide defects have given high accelerating factors γ of 11-12, revealing the excellent reliability of the gate stacks. We have attained low Dit’s and small charge trapping in the Ge (100) and (110) gate stacks with the combination of direct high-κ deposition and low-temperature grown epi-Si, without a high-pressure annealing.

Keywords: Ge, epi-Si, high mobility channel , metal-oxide-semiconductor, interfacial trap density